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Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 19 of 26

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5693R/AD5692R/AD5691R/AD5693 are single 16-bit,

14-bit, and 12-bit, serial input, voltage output DACs with a 2.5 V

internal reference. The devices operate from supply voltages of 2.7 V

to 5.5 V. Data is written to the AD5693R/AD5692R/AD5691R/

AD5693 in a 24-bit word format via an I2C serial interface.

The AD5693R/AD5692R/AD5691R/AD5693 incorporate a

power-on reset circuit that ensures that the DAC output powers up

to zero scale. The devices also have a software power-down mode

that reduces the current consumption to 2 µA maximum.

TRANSFER FUNCTION

The internal reference is on by default. The input coding to the

DAC is straight binary. The ideal output voltage is given by the

following equations:

For the AD5693R/AD5693,

VOUT(D) = Gain × VREF ×













536

For the AD5692R,

VOUT(D) = Gain × VREF ×













384

For the AD5691R,

VOUT(D) = Gain × VREF ×













4096

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register.

Gain is the gain of the output amplifier and it is set to ×1 by

default. The gain can also be set to ×2 using the gain bit in the

control register.

DAC ARCHITECTURE

The AD5693R/AD5692R/AD5691R/AD5693 implement a

segmented string DAC architecture with an internal output buffer.

Figure 45 shows the internal block diagram.

INPUT

DAC

2.5V

REF

RESISTOR

STRING

REF (+)

REF (–)

GND

VOUT

VREF

Figure 45. DAC Channel Architecture Block Diagram

The simplified segmented resistor string DAC structure is

shown in Figure 46. The code loaded to the DAC register

determines the switch on the string that is connected to the

output buffer.

Because each resistance in the string has same value, R, the

string DAC is guaranteed monotonic.

TO OUTPUT

BUFFER

VREF

Figure 46. Simplified Resistor String Structure

Internal Reference

The AD5693R/AD5692R/AD5691R on-chip reference is on at

power-up but can be disabled via a write to the control register.

The AD5693R/AD5692R/AD5691R each have a 2.5 V, 2 ppm/°C

reference, giving a full-scale output of 2.5 V or 5 V, depending

on the state of the gain bit.

The internal reference is available at the VREF pin. It is internally

buffered and capable of driving external loads of up to 5 mA.

External Reference

The VREF pin is an input pin in the AD5693. The VREF pin can also

be configured as an input pin on the AD5693R/AD5692R/

AD5691R, allowing the use of an external reference if the

application requires it.

In the AD5693R/AD5692R/AD5691R, the default condition of

the on-chip reference is on at power-up. Before connecting an

external reference to the pin, disable the internal reference by

writing to the REF bit (Bit DB12) in the control register.

Output Buffer

The output buffer is designed as an input/output rail-to-rail

buffer, which gives a maximum output voltage range of up to

VDD. The gain bit sets the segmented string DAC gain to ×1 or

×2, as shown in Table 14.

The output buffer voltage is determined by VREF, the gain bit,

and the offset and gain errors.

The output buffer can drive a 10 nF capacitance with a 2 kΩ

resistor in parallel, as shown in Figure 39 and Figure 42. If

a higher capacitance load is required, use the snubber method

or a shunt resistor to isolate the load from the output amplifier.

The slew rate is 0.7 V/µs with a ¼ to ¾ scale settling time of 5 µs.

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