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AD5693R/AD5692R/AD5691R/AD5693

Data Sheet

Rev. D | Page 20 of 26

SERIAL INTERFACE

The AD5693R/AD5692R/AD5691R/AD5693 have 2-wire, I2C-

compatible serial interfaces. These devices can be connected to

an I2C bus as a slave device, under the control of a master

device. See Figure 3 for a timing diagram of a typical write

sequence.

The AD5693R/AD5692R/AD5691R/AD5693 support standard

(100 kHz) and fast (400 kHz) data transfer modes. Support is

not provided for 10-bit addressing and general call addressing.

I2C SERIAL DATA INTERFACE

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the 9th clock pulse (this is

called the acknowledge (ACK) bit). At this stage, all other

devices on the bus remain idle while the selected device

waits for data to be written to, or read from, its shift

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10th clock pulse, and then high during the 10th

clock pulse to establish a stop condition.

I2C ADDRESS

The AD5693R/AD5692R/AD5691R/AD5693 have a 7-bit slave

address. The five MSBs are 10011. The second last bit set by the

state of the A0 address pin and the LSB is 0. The ability to make

hardwired changes to A0 lets the user have two of these devices

on one bus, as outlined in Table 11. Additionally, the pin can be

updated before starting the transmission, allowing multiple

devices in the same bus by connecting the pin to a GPIO or a

multiplexer.

Table 11. Device Address Selection

A0 Pin Connection

I2C Address

GND

1001100

VLOGIC (VDD on LFCSP Package)

1001110

WRITE OPERATION

When writing to the AD5693R/AD5692R/AD5691R/AD5693,

the user must begin with a start condition followed by an address

byte (R/W = 0), after which the DAC acknowledges that it is pre-

pared to receive data by pulling SDA low, as shown in Figure 47.

The AD5693R/AD5692R/AD5691R/AD5693 require a

command byte that controls various DAC functions (see Table 12)

and two bytes of data for the DAC. All these data bytes are

acknowledged by the AD5693R/AD5692R/AD5691R/AD5693. A

stop condition follows. The write sequence is shown in Figure 47.

SCL

SDA

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 3

DATA HIGH BYTE

FRAME 4

DATA LOW BYTE

FRAME 2

COMMAND BYTE

ACK BY

AD5693R/AD5692R/AD5691R/AD5693

ACK BY

AD5693R/AD5692R/AD5691R/AD5693

ACK BY

AD5693R/AD5692R/AD5691R/AD5693

STOP BY

MASTER

ACK BY

AD5693R/AD5692R/AD5691R/AD5693

SCL

(CONTINUED)

SDA

(CONTINUED)

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R/W

Figure 47. I2C Write Operation

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