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Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 23 of 26

LOAD DAC (HARDWARE LDAC PIN)

The AD5693R/AD5692R/AD5691R/AD5693 DAC has a double

buffered interface consisting of an input register and a DAC

the DAC register, and the output is updated.

Synchronous DAC Update

If the LDAC pin is held low while the input register is written,

the DAC register, input register, and output are updated on the

last SCL falling edge before the ACK bit, as shown in Figure 4.

Asynchronous DAC Update

LDAC is held high while data is transmitted to the device. The

DAC output is updated by taking LDAC low after the stop

condition has been generated. The output DAC is updated on

the falling edge of the LDAC pin. If LDAC is pulsed while the

device is accessed, the pulse is ignored.

HARDWARE RESET

RESET is an active low signal that resets the DAC output to zero-

scale and sets the input, DAC, and control registers to their

default values. It is necessary to keep RESET low for 75 ns to

complete the operation. When the RESET signal is returned high,

the output remains at zero scale until a new value is programmed.

While the RESET pin is low, the AD5693R/AD5692R/AD5691R/

AD5693 ignore any new command. If the RESET pin is held

low at power-up, the internal reference is not initialized

correctly until the RESET pin is released.

THERMAL HYSTERESIS

Thermal hysteresis is the voltage difference induced on the

reference voltage by sweeping the temperature from ambient

to cold, to hot, and then back to ambient.

The thermal hysteresis data is shown in Figure 50. It is measured by

sweeping the temperature from ambient to −40°C, then to +105°C,

and finally returning to ambient. The VREF delta is measured

between the two ambient measurements; the result is shown in

solid lines in Figure 50. The same temperature sweep and

measurements were immediately repeated; the results are

shown in dashed lines in Figure 50.

–100

–20

–60

–40

–80

DISTORTION (ppm)

FIRST TEMPERATURE SWEEP

SUBSEQUENT SWEEPS

Figure 50. Thermal Hysteresis

POWER-UP SEQUENCE

Because diodes limit the voltage compliance at the digital pins

and analog pins, it is important to power GND first before

applying any voltage to VDD, VOUT, and VLOGIC. Otherwise, the

diode is forward-biased such that VDD is powered uninten-

tionally. The ideal power-up sequence is GND, VDD, VLOGIC,

VREF, followed by the digital inputs.

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