33
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
1: force SD signal OK in 100M
0: normal SD singal.
20.12
TSTSEL3
0,RW
Vendor test select control
20.11-20.
8
Reserved
0, RO
Reserved
Read as 0, ignore on write
20.7
MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value
1: MDIX mode
0: MDI mode
20.6
AutoNeg_dpbk
0,RW
Auto-negotiation loopback
1: test internal digital auto-negotiation loopback
0: normal.
20.5
Mdix_fix Value
0, RW
MDIX_CNTL force value:
When MDIX_DOWN = 1, MDIX_CNTL value depend on the register
value.
20.4
Mdix_do wn
0,RW
MDIX Down
Manual force MDI/MDIX.
0: Enable auto MDI/MDIX
1: Disable auto MDI/MDIX, MDIX_CNTL value depend on 20.5
20.3
MonSel1
0,RW
Vendor monitor select
20.2
MonSel0
0,RW
Vendor monitor select
20.1
RMII_Ver
0,RW
RMII version
0: support RMII 1.2
1: support RMII 1.0
20.0
PD_value
0,RW
Powerdown control value
Decision the value of each field Register 19.
1: powerdown
0: normal
8.13 DAVICOM Specified Interrupt Register – 21
Bit
Bit Name
Default
Description
21.15
INTR PEND
0, RO
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
21.14-21.
12
Reserved
0, RO
Reserved
21.11
FDX mask
1, RW
Full-duplex Interrupt Mask
When this bit is set, the Duplex status change will not generate the
interrupt
21.10
SPD mask
1, RW
Speed Interrupt Mask
When this bit is set, the Speed status change will not generate the
interrupt
21.12
LINK mask
1, RW
Link Interrupt Mask
When this bit is set, the link status change will not generate the
interrupt
21.8
INTR mask
1, RW
Master Interrupt Mask
When this bit is set, no interrupts will be generated under any
condition
21.7-21.5
Reserved
0, RO
Reserved
21.4
FDX change
0,RO/LH
Duplex Status Change Interrupt
“1” indicates a change of duplex since last register read. A read of
this register will clear this bit
21.3
SPD change
0, RO/LH
Speed Status Change Interrupt
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