AX88178 datasheet(6/35 Pages) ASIX

6 / 35 page

ASIX ELECTRONICS CORPORATION

AX88178 L

USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller

TX_CLK

102

Transmit Clock in MII mode. TX_CLK is received from PHY to

provide timing reference for the transfer of TXD [3:0], TX_EN and

TX_ER signals on transmit direction of MII interface.

GTX_CLK

Transmit Clock in GMII mode. GTX_CLK is output to PHY to

provide timing reference for the transfer of TXD [7:0], TX_EN and

TX_ER signals on transmit direction of GMII interface.

TXC

Transmit Clock in RGMII mode. TXC is output to PHY to provide

timing reference for the transfer of TXD [3:0], and TX_EN signals on

transmit direction of RGMII interface.

TXD [7:0]

76, 77, 78,

79, 82, 83,

84, 85

Transmit Data. TXD [7:0] is transitioned synchronously with respect

to the rising edge of GTX_CLK in GMII mode or rising edge of

TX_CLK in MII mode. In RGMII mode, only TXD [3:0] is used and

is transitioned synchronously with respect to TXC clock output pin.

TX_EN

Transmit Enable. TX_EN is transitioned synchronously with respect

to the rising edge of GTX_CLK in GMII mode or rising edge of

TX_CLK in MII mode. TX_EN is asserted high to indicate a valid

TXD [7:0]. In RGMII mode, TX_EN acts as TX_CTL and is

transitioned synchronously with respect to TXC clock output pin.

TX_ER

Transmit Coding Error. TX_ER is transitioned synchronously with

respect to the rising edge of GTX_CLK in GMII mode or rising edge

of TX_CLK in MII mode. When asserted high for one or more

GTX_CLK/TX_CLK, the PHY shall emit one or more code-groups

that are not part of the valid data or delimiter set somewhere in the

frame being transmitted.

Serial EEPROM Interface

EECK

EEPROM Clock. EECK is an output clock to EEPROM to provide

timing reference for the transfer of EECS, EEDI, and EEDO signals.

The frequency of EECK is 187.5Khz.

EECS

EEPROM Chip Select. EECS is asserted high synchronously with

respect to rising edge of EECK as chip select signal.

EEDI

EEPROM Data In. EEDI is the serial output data to EEPROM’s data

input pin and is synchronous with respect to the rising edge of EECK.

EEDO

I5/PD

EEPROM Data Out. EEDO is the serial input data from EEPROM’s

data output pin.

Misc. Pins

XIN125M

101

125Mhz clock input. Connect to a 125Mhz free run clock source

when in GMII or RGMII mode. In MII mode, connect to GND

through a pull-down resistor.

RESET_N

I5/PU/S

Chip Reset Input. RESET_N pin is active low. When asserted, it puts

the entire chip into reset state immediately. After completing reset,

EEPROM data will be loaded automatically.

EXTWAKEUP_N I5/PU/S

Remote-wakeup trigger from external pin. EXTWAKEUP_N should

be asserted low for more than 2 cycles of 12MHz clock to be

effective.

GPIO [2:0]

B5/PD

1, 2, 3

General Purpose Input/ Output Pins. These pins are default as input

pins after power-on reset. Please use GPIO0 for controlling the power

down pin of external Ethernet Phy.

PHYRST_N

122

PHYRST_N is a tri-stateable output used for resetting external

Ethernet PHY. This pin is default in tri-state after power-on reset. If

external Ethernet PHY’s reset level is active low, connect this to

PHY’s reset pin with a pulled-down resistor. If it’s active high,

connect this to PHY with a pulled-up resistor. This way can make sure

the external Ethernet PHY stays in reset state before software brings it

out of reset.

RGMII_EN

I3/PD

103

RGMII mode Enable. Setting this pin high sets the Ethernet PHY

interface into RGMII mode. Setting this pin low sets the Ethernet

PHY interface into MII or GMII mode.

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