PM25LD010 datasheet(5/33 Pages) ETC2

5 / 33 page

Pm25LD512/010/ 020

Confidential information

Chingis Technology Corp.

DRAFT Date: August, 2010, Rev:0.4

SPI MODES DESCRIPTION

Multiple Pm25LD512/010/020 devices can be

connected on the SPI serial bus and controlled by a

SPI Master, i.e. microcontroller, as shown in Figure 1.

The devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock

polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and

the clock remains at “1” (SCK = 1) for Mode 3. Please

refer to Figure 2. For both modes, the input data is

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

Figure 2. SPI Modes Supported

MSb

SCK

SIO

Input mode

Mode 0 (0, 0)

Mode 3 (1, 1)

SPI Master

(i.e. Microcontroller)

CS3

CS2

CS1

SPI Memory

Device

SPI Memory

Devic

SPI Memory

Device

SPI Interface with

(0,0) or (1,1)

SDIO

SDI

SCK

SIO

CE#

WP#

HOLD#

Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

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