LD5857

9

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5857-DS-00 April 2014

Current

Sensing

and

Leading-edge

Blanking

The LD5857 detects the primary MOSFET current

across CS pin for the protection of cycle-by-cycle

current limit. The voltage threshold of the current

sensing pin is set at 0.45V maximum. The MOSFET

peak current can be obtained as below.

CS

)

MAX

(

PEAK

R

V

45

.

0

I



A 275ns leading-edge blanking (LEB) time is set in CS

pin to prevent the false-triggering from the current spike.

The R-C filter is eliminable in those low power

applications, for LD5857 features pulse width of the

turn-on spikes below 275ns and the negative spike of

the CS pin below -0.5V.

However, the pulse width of the turn-on spike is

determined according to the output power, circuit design

and PCB layout.

It is strongly recommended to add a

smaller R-C filter for large power application to avoid CS

pin from being damaged by the negative turn-on spike.

CS

Removable if the negative

Spike is not over spec (-0.5V)

DRV

275ns

blanking

time

OCP

Signal

0.45V

Fig. 9

equation to avoid the output power from being clamped

V

5

.

3

)

R

I

3

(

)

Duty

3

.

1

(

5

.

1

CS

)

Peak

(

L

(%)













x3

Sense

Amplifier

EA

S

CS

COMP

FB

Fig. 10

Thermal Protection

Thermal protection limits the whole power dissipation in

this device. When the junction temperature reaches

150

C, the thermal sensor will send a signal of

shutdown logic to disable the device and would not

resume operation unless

the IC’s junction temperature

cools down for 30°C

PCB Layout Guideline

It’s recommended to separate the high frequency

switching current from the low-level control signals in

layout. The high switching current (MOSFET, inductor,

gate driver and FB return ends) may disturb the

low-level signals in the feedback loop and protection

circuitry. As a result, it may cause the control function to

behave abnormally. To avoid these side effects, a few

guidelines are recommended for the PCB layout as

below.

1. Route the VIN bypass capacitor and the signal

ground close to the IC as possible. The traces

between capacitor and VIN pin should be short as

possible to avoid noise interference.

2. Use broader traces for VIN, VOUT and power

ground. Those components connected to VIN,

VOUT and power ground carry high input/output

current, such as power MOSFET and decoupling

capacitors. To minimize power loss in these traces,

the resistance of traces should be kept as low as

possible.