GS3471 datasheet(129/179 Pages) SEMTECH

129 / 179 page

GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

129 of 179

Semtech

www.semtech.com

86B

PLL_STAT

RSVD

15:10

—

Reserved.

PLLSM_CDRSEL

9:9

Unforced CDRSEL output:

0 = The device is using the clock as



reference



1 = The device is using data as reference

PLLSM_LOCK

8:8

Unforced LOCK output.

LOS

7:7

Loss of signal indicator. Inverse of

CARRIER_DETECT.

PHASELOCK_ANALOG

6:6

Output of analog lock detector.

PLD_PHASELOCK_

DIGITAL

5:5

Output of digital phaselock detector.

CD_CARRIER_DETECT

4:4

Unforced CARRIER_DETECT signal (after

MUX).

CD_DIGIAL_FILT

3:3

Filtered digital carrier detect status:

0 = The edge detection circuit is not



detecting data



1 = The edge detection circuit is detecting



data

CD_ANALOG_FILT

2:2

Filtered analog carrier detect status:

0 = When LOW, the LOS circuit is not



detecting data



1 = When HIGH the LOS circuit is



detecting data

RSVD

1:0

—

Reserved.

86C

PLL_STICKY_

STAT

RSVD

15:7

—

Reserved.

LOCK_LOST_STICKY

6:6

ROCW

Sticky bit for loss of lock indicator. Inverse

of LOCK output.

PHASELOCK_

LOST_STICK

5:5

ROCW

Sticky bit for loss of phaselock indicator.

Inverse of phaselock output from

PHASE_DETECTOR.

LOS_STICKY

4:4

ROCW

Sticky bit for loss of signal indicator (after

MUX). Inverse of CARRIER_DETECT.

RSVD

3:0

ROCW

—

Reserved.

Table 5-9: Video Core CSR Descriptions (Continued)

Addressh

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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