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GS3471 Datasheet(PDF) 131 Page - Semtech Corporation

Part # GS3471
Description  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 Datasheet(HTML) 131 Page - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
131 of 179
Semtech
www.semtech.com
870
DELAY_LINE_
CTRL_1
RSVD
15:15
—
—
Reserved.
PCLK_DELAY_SD
14:10
RW
0
Controls the offset for the delay line in SD:
00000b = No delay
11111b = Max delay
Step Size = 0.006 UI
PCLK_DELAY_HD
9:5
RW
0
Controls the offset for the delay line in HD:
00000b = No delay
11111b = Max delay
Step Size = 0.031 UI
PCLK_DELAY_3G
4:0
RW
0
Controls the offset for the delay line in 3G:
00000b = No delay
11111b = Max delay
Step Size = 0.031 UI
871
DELAY_LINE_
CTRL_2
RSVD
15:3
—
—
Reserved.
PCLK_INVERT_SD
2:2
RW
0
Controls the inversion of PCLK in SD.
PCLK_INVERT_HD
1:1
RW
0
Controls the inversion of PCLK in HD.
PCLK_INVERT_3G
0:0
RW
0
Controls the inversion of PCLK in 3G.
872 to 873
RSVD
RSVD
15:0
—
—
Reserved.
874
CLK_GEN
RSVD
15:3
—
—
Reserved.
DDR_PHASE_
DET_INVERT
2:2
RW
1
Swaps the phase in DDR mode.
User can choose whether to start data
transmission from a rising edge or a falling
edge of the DDR clock.
RSVD
1:1
RW
0
Reserved.
SD_HD_DDR_SEL
0:0
RW
0
Enables DDR mode for SD, HD, and
non-SMPTE data if DDR is supported for
that specific rate.
875
PD_CTRL
RSVD
15:12
—
—
Reserved.
POL_INV
11:11
RW
0
Phase Detector Polarity Invert:
0 = PD uses normal data polarity
1 = PD uses inverted data polarity
RSVD
10:0
—
—
Reserved.
876
RSVD
RSVD
15:0
—
—
Reserved.
Table 5-9: Video Core CSR Descriptions (Continued)
Addressh
Register Name
Parameter Name
Bit
Slice
R/W
Reset
Valueh
Description



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