GS3471 datasheet(127/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

127 of 179

Semtech

www.semtech.com

84A

ERROR_

MASK_3

RSVD

15:14

—

Reserved.

ERROR_MASK_DS2

13:0

Error mask for global error vector - DS2

triggers (sticky and non-sticky):

[13] = Chroma channel ancillary data

checksum error mask (non-sticky version)



[12] = Luma channel ancillary data

checksum error mask (non-sticky version)



[11] = Chroma channel CRC error mask

(non-sticky version)



[10] = Luma channel CRC error mask

(non-sticky version)



[9] = Line number error mask (non-sticky

version)



[8] = SAV error mask (non-sticky version)



[7] = EAV error mask (non-sticky version)



[6] = Chroma channel ancillary data

checksum error mask (sticky version)



[5] = Luma channel ancillary data

checksum error mask (sticky version)



[4] = Chroma channel CRC error mask

(sticky version)



[3] = Luma channel CRC error mask (sticky

version)



[2] = Line number error mask (sticky

version)



[1] = SAV error mask (sticky version)



[0] = EAV error mask (sticky version)

84B

ACG_CTRL

RSVD

15:6

—

Reserved.

AUDIO_FREE_RUN

5:5

0 = Audio digital PLL runs in acquisition

mode and tries to lock to REF_CLK



1 = Audio digital PLL runs in free run

mode and ignores the REF_CLK

SCLK_INV

4:4

When HIGH, inverts polarity of output

serial audio clock.

AMCLK_INV

3:3

When HIGH, inverts polarity of output

audio master clock.

RSVD

2:2

Reserved.

AMCLK_SEL

1:0

Audio Master Clock (AMCLK) select:

00b = 128fs

01b = 256fs

10b = 512fs

84C

RSVD

15:0

—

Reserved.

Table 5-9: Video Core CSR Descriptions (Continued)

Addressh

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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