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GS3471 Datasheet(PDF) 174 Page - Semtech Corporation

Part # GS3471
Description  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 Datasheet(HTML) 174 Page - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
174 of 179
Semtech
www.semtech.com
6.2 Layout Considerations
General best practices for high-speed board layout should be followed when designing
with the GS3471. These general best practices can be found in a number of Semtech
design guides including:
•
GS3471 Receiver Design Guide (TBD)
•
GS2972 Transmitter Design Guide (GENDOC-048581)
•
Multi-Gigabit Serial Routing Products (PDS-060967)
•
GS2989 Cable Driver Design Guide (GENDOC-052070)or most recent CD design
guide available
The following layout considerations are specific to the GS3471:
•
GS3471's analog supplies, particularly its 1.2V VCC supply, are sensitive to noise. For
optimal performance, it is recommended that the power supplies are isolated to
avoid external noise coupling. DDI_VDD and DDO_VDD may be combined if they
are powered at the same supply level. However, PLL_VDD, CORE_VDD and
IO_VDD should be routed separately.
•
Linearly regulated power supplies are recommended wherever possible as they
provide the cleanest power.
•
Critical components such as power supply decoupling capacitors, LF capacitor,
RBIAS resistor, CT0 and CT1 capacitors and VCO filter should be placed as close as
possible to the GS3471.
•
DDI/DDI, SDI/SDI, and DDO/DDO differential inputs and outputs should be routed
using 100Ω differential controlled impedance transmission lines.
•
When paired with a compatible cable equalizer or cable driver, it is possible to
DC-couple the differential high-speed inputs and outputs. In cases requiring
AC-coupling, anti-pads should be used underneath AC-coupling capacitors to
minimize the parasitic capacitance associated with these components. Details on
the use of anti-pads can be found in the Semtech video design guides referenced
above.
•
The parallel data outputs and timing signals should be electrically phase matched
to within 1/20th of a wavelength. For 300MHz, this is approximately equivalent to
1" of FR4 micro-strip.
•
Serial termination on the parallel data outputs and timing signals may be required
for very long traces or traces going through connectors.



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