GS3471 datasheet(171/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

171 of 179

Semtech

www.semtech.com

INT_OUT_

CONF_REG_0

RSVD

15:11

Reserved. Do not change.

DATA_RATE_

DETECTION

10:6

Data Rate Detection Enable. Selects which

data rates will be reported on EQ_STAT,

which is available on the STAT[5:0] pins

when INT_SOURCE_SELECT is set to 100b or

101b. Set the corresponding bit to 1 to

enable detection reporting for each rate.

Bit 0 = Reserved



Bit 1 = Reserved



Bit 2 = SD



Bit 3 = HD



Bit 4 = 3G

INT_SOURCE_

SELECT

5:3

Selects the interrupt signal source.

000b = Filtered or unfiltered EQ carrier

detect



001b = AFE_RD_CD_MUX_OUT (carrier

detect as selected by

INT_CD_MODE_SELECT)



010b = Reserved

011b = Rate change detect

100b = CD and rate detect for rates selected

with DATA_RATE_DETECTION



101b = CD and rate detect for rates selected

with DATA_RATE_DETECTION with low

pulse on rate change.



110b, 111b = Reserved

INT_CD_

MODE_SELECT

2:0

Carrier Detect Mode

000b = General Carrier Detect (CD) (any rate)

001b = Reserved

010b = Reserved

011b = CD for SD

100b = CD for HD

101b = CD for 3G

110b, 111b = Reserved

A to 7E

RSVD

15:0

—

Reserved. Do not change.

Table 5-13: Equalizer Register Descriptions

Addressh

Parameter Name

Bit

R/W

Reseth

Description

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