GPBA01B datasheet(6/29 Pages) GENERALPLUS

6 / 29 page

GPBA01B

Proprietary & Confidential

MAY 28, 2007

Version: 1.1

6. FUNCTIONAL DESCRIPTIONS

6.1. The Easiest System

Bus extender (BEX) plays a role as an interface between MPU

(GPLB31, GPL131…) and general-purposed (third-party) memory

products.

In fact, the BEX is a bus translator that translates the

AD bus of BMI

tm to the general-purposed memory bus.

Below figure show the easiest way to use GPBA01B, the MPU

send 11 signals to GPBA01B, GPBA01B latch the address and

then send it to AT29C040 flash memory, GPBA01B also have

responsibility to generate CE , OE , WE to the memory.

read cycle, the memory output the data at the common bus

(AD7-AD0); while write cycle, GPL131 drive the written-data to

AD7-AD0.

The

bus

(AD7-AD0)

may

Address

High-Byte

(AH),

Address-Low-Byte (AL) and 8-bit bi-direction data.

Also, the AD

bus is common for MPU, GPBA01B, and memory.

All of these

may drive the bus depending on MC1, MC0 status.

MC[1:0]

AD[7:0]

GPBA01B

OUT

MC[1:0]

AD[7:0]

MPU

AT29C040

D[7:0]

A[21:0]

Flash

Memory

GPL131/GPLB31,...)

6.2. Address/Data Bus Control

The GPBA01B (Bus extender) is a bridge between MPU

(GPL130A,

GPLB31A…)

and

general-purposed

(third-party)

memory products. The MC1 and MC0 are the control signals for

AD7-AD0, which can be three states: Address High-Byte (AH),

Address-Low-Byte (AL) and 8-bit bi-direction data.

When MC1 is high, AD [7:0] functions as an address-bus,

otherwise the AD [7:0] becomes a data-bus.

In address-bus

mode, AD [7:0] signifies high-address, A [15:8], when MC0 is high;

in contrast, AD [7:0] expresses low-address, A [7:0], when MC0 is

low.

In data-bus mode, AD [7:0] represents data, D [7:0], which

will be read from CPU when MC0 is high and CPU writes data to

AD [7:0] when MC0 is low.

P0, P1, P2, WE , OE can be utilized as address-line, chip-enable,

output-enable or write-enable for addressing external memory chip

(please

refer

Bus

Extender

Assignment

for

configurations

The number of pins needed for addressing

depends on configuration and the remaining pins used for I/O port.

When

used

memory

extender,

chip-enable

( CE ),

output-enable ( OE ) and write-enable ( WE ) operate in negative

logic (voltage low stands for active, and voltage high stands for

inactive).

The address lines include A [14:0] (presenting CPU

address) and B [6:0] (presenting bank register).

6.2.1. Decode table

MC1 decides AD bus to be address or data bus, and MC0 decides

operation mode (Read or Write).

MC1

MC0

AD BUS

Data for Read

Data for Write

6.2.2. Timing relations between control signals, AH, AL

and data.

MC0

Read Cycle:

MC1

DATA for read

Write Cycle:

MC0

MC1

DATA for write

GPBA01B Datasheet(PDF) 6 Page - Generalplus Technology Inc.

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