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AM5728 Datasheet(PDF) 271 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 271 Page - Texas Instruments |
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271 / 415 page  25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop I2Ci_SDA I2Ci_SCL 16 26 24 271 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-36 and Figure 7-24 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 7-36. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2) NO. PARAMETER DESCRIPTION STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs 17 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 18 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns 22 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45 0 0.9 µs 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (1) (3) 300(3) ns 25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (1) (3) 300(3) ns 26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (1) (3) 300(3) ns 27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (1) (3) 300(3) ns 28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF (1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. (2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details. (3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, and I2C5 use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. NOTE I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic-1. Figure 7-24. I2C Transmit Timing |
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