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AM5728 Datasheet(PDF) 272 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 272 Page - Texas Instruments |
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272 / 415 page  HDQ t HW1 t HW0 t CYCH Vayu_HDQ1W_02 HDQ t B t BR Vayu_HDQ1W_01 272 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated 7.13 HDQ / 1-Wire Interface (HDQ1W) The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to communicate between the master and the slave. The protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high. NOTE For more information, see the HDQ / 1-Wire section of the Device TRM. 7.13.1 HDQ / 1-Wire — HDQ Mode Table 7-37 and Table 7-38 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-25, Figure 7-26, Figure 7-27, and Figure 7-28). Table 7-37. HDQ/1-Wire Timing Requirements—HDQ Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tCYCH Read bit window timing 190 250 µs 2 tHW1 Read one data valid after HDQ low 32(2) 66(2) µs 3 tHW0 Read zero data hold after HDQ low 70(2) 145(2) µs 4 tRSPS Response time from HDQ slave device(1) 190 320 µs (1) Defined by software. (2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see Table 7-38 and the HDQ/1-Wire chapter of the TRM. Table 7-38. HDQ / 1-Wire Switching Characteristics - HDQ Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT 5 tB Break timing 190 µs 6 tBR Break recovery time 40 µs 7 tCYCD Write bit windows timing 190 µs 8 tDW1 Write one data valid after HDQ low 0.5 50 µs 9 tDW0 Write zero data hold after HDQ low 86 145 µs Figure 7-25. HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave Figure 7-26. Device HDQ Interface Bit Read Timing (Data) |
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