AM5728 datasheet(385/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

vias is permitted on the same side of the board.

(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the

connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s

guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.

(12) For more information, see , Core Power Domains

8.2.2.10.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. Because these are returns for signal current, the signal via size may be used for these

capacitors.

8.2.2.11 Net Classes

Table 8-10 lists the clock net classes for the DDR3 interface. Table 8-11 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-10. Clock Net Class Definitions

CLOCK NET CLASS

processor PIN NAMES

ddrx_ck / ddrx_nck

DQS0

ddrx_dqs0 / ddrx_dqsn0

DQS1

ddrx_dqs1 / ddrx_dqsn1

DQS2(1)

ddrx_dqs2 / ddrx_dqsn2

DQS3(1)

ddrx_dqs3 / ddrx_dqsn3

(1) Only used on 32-bit wide DDR3 memory systems.

Table 8-11. Signal Net Class Definitions

SIGNAL NET CLASS

ASSOCIATED CLOCK

NET CLASS

processor PIN NAMES

ADDR_CTRL

ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,

ddrx_cke, ddrx_odti

DQ0

DQS0

ddrx_d[7:0], ddrx_dqm0

DQ1

DQS1

ddrx_d[15:8], ddrx_dqm1

DQ2(1)

DQS2

ddrx_d[23:16], ddrx_dqm2

DQ3(1)

DQS3

ddrx_d[31:24], ddrx_dqm3

(1) Only used on 32-bit wide DDR3 memory systems.

8.2.2.12 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.2.2.13 VREF_DDR Routing

ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the

processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the

DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF

bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing

congestion.

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