SDA

SCL

S

P

Start Cond itio n

Stop Condition

Data Li ne

Stable;

Data V alid

Chang e

of Data

Allo wed

SDA

SCL

16

LP5009, LP5012

SLVSEH2 – MAY 2019

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Copyright © 2019, Texas Instruments Incorporated

8.5 Programming

device. This protocol uses a two-wire interface for bidirectional communications between the devices connected

to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on

the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates

or receives the serial clock, SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere

on the line and remain HIGH even when the bus is idle.

8.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state

of the data line can only be changed when the clock signal is LOW.

Figure 9. Data Validity

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition

is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is

defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates

START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP

condition. During data transmission, the bus master can generate repeated START conditions. First START and

repeated START conditions are functionally equivalent.

Figure 10. Start and Stop Conditions