ADF41513 datasheet(12/30 Pages) AD

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ADF41513

Data Sheet

Rev. 0 | Page 12 of 30

Variable Modulus (R0, DB28 = 1)

For the variable modulus, the RF VCO frequency (RFOUT)

equation is

RFOUT = fPFD × (INT + (FRAC1 + (FRAC2/MOD2))/225) (3)

where:

RFOUT is the output frequency of external VCO.

INT is a 16-bit value set by Bits[19:4] in Register 0. In Integer N

mode, INT is 20 to 511 for a 4/5 prescaler and 64 to 1023 for a 8/9

prescaler, and in fractional-N mode, INT is 23 to 511 for a 4/5

prescaler and 75 to 1023 for a 8/9 prescaler.

FRAC1 is a 25-bit value set by Bits[28:4] in Register 1.

FRAC2 is a 24-bit value set by Bits[27:4] in Register 3.

MOD2 is a 24-bit value set by Bits[27:4] in Register 4.

The minimum RF output resolution is set by fPFD/249. Therefore,

for fPFD = 100 MHz, the minimum resolution is 0.1776 µHz. To

achieve this resolution, MOD2 must be set to its maximum of

(224− 1), which is 16,777,215.

Integer N Mode

When FRAC1 and FRAC2 are both equal to 0, the ADF41513

can operate in purely integer N mode, which improves the

phase noise performance of the PLL and sets the frequency

resolution to fPFD. This feature is not automatic and must be

manually set for Integer N channels. Bleed must also be

disabled when using the ADF41513 in Integer N operation. See

the Register 12 (R12) Map section for more information on

programming the ADF41513 for Integer N operation.

R COUNTER

The 5-bit R counter allows REFIN to be divided down to produce

the reference clock to the PFD. Division ratios from 1 to 32 are

allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between these inputs. Figure 18 shows a PFD simplified

schematic. The PFD includes a fixed delay element that sets the

width of the antibacklash pulse, which is typically 1 ns. This pulse

ensures that there is no dead zone in the PFD transfer function

and produces a consistent reference spur level.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 18. PFD Simplified Schematic

MUXOUT

The output multiplexer on the ADF41513 allows the user to access

various internal nodes on the chip. The M4, M3, M2, and M1 bits

in Register 12 (see the Register 12 (R12) Map section) controls

the state of MUXOUT. Figure 19 shows the MUXOUT section in

block diagram form. Many of these access points are useful for

debugging. For example, select the N divider output to check if

the N divider is functioning correctly. Most of the access points

are self explanatory. Set the CLK1 divider output signal to access

the internal CLK1 divider signal used for phase resync. During

power-down (CE = logic low), MUXOUT is set to GND.

THREE-STATE OUTPUT

DGND

R-DIVIDER OUTPUT

N-DIVIDER OUTPUT

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

CLK DIVIDER OUTPUT

R-DIVIDER/2

MUX

CONTROL

MUXOUT

AVDD5

DGND

N-DIVIDER/2

READBACK TO MUXOUT

AVDD5

Figure 19. MUXOUT Schematic

LOCK DETECTOR

The lock detector compares the PFD output pulse width against

a lock detector window. Measurements are performed every

PFD comparison cycle when LD_CLK_SEL = 0 or every 32nd

cycle when LD_CLK_SEL = 1. If the pulse width falls within the

lock window, a counter is incremented. If the counter reaches

the count set by LD_COUNT without an up or down pulse

width exceeding the lock detect window and without a cycle slip

occurring, lock is then declared by the lock detector.

When the lock detector has declared lock, the main mechanism

to declare a loss of lock is for a cycle slip to occur. This cycle slip

is usually caused by a frequency error at the phase detector

input, causing the phase error to grow until the error exceeds

360°. The phase error then wraps around to 0°. This phase wrap

around is a cycle slip.

A high level on MUXOUT indicates the PLL is in lock.

The lock detector window size, LD_COUNT, and

LD_CLK_SEL all affect the sensitivity of the lock detector.

Larger windows, smaller LD_COUNT values, and

LD_CLK_SEL = 0 shorten the overall lock detect time and

increase sensitivity. Smaller windows, larger LD_COUNT

values, and LD_CLK_SEL = 1 increase the overall lock detect

time and reduce sensitivity. Excessive lock detector sensitivity

can cause multiple transitions between a locked state and out of

lock state during frequency changes. Insufficient lock detector

sensitivity can cause the detector to indicate an out of lock state

when, in fact, the PLL is locked.

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