ADF41513

Data Sheet

Rev. 0 | Page 26 of 30

REGISTER 12 (R12) MAP

MUXOUT

Register 12, Bits[31:28] select the MUXOUT signal. Register

data can be read either by selecting the serial data output or via

a readback. Serial data output sends the 32 bits of register data

that was written in the previous access. A readback sends the

data as defined by the readback select bits, Register 12,

Bits[19:14].

Logic Level

Register 12, Bit 27 selects the DLD and MUXOUT logic level.

Master Reset

Register 12, Bit 22 = 1 resets all registers to all zeros.

LE Select

Register 12, Bit 20 = 1 synchronizes the rising edge of LE on an

SPI write with the falling edge of the reference signal. This recom-

mended setting ensures there is no glitch from asynchronous

loading. Set Register 12, Bit 20 = 0 if it is necessary to write data

into the ADF41513 when no reference is present.

Readback Select

Register 12, Bits[19:14] select the value to be read back. For

more information, see the Readback section.

DB31

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3 DB2

DB1

DB0

M4

M3

M2

M1

0

0

0

0

0

LL

MR1

L1

R6

R5

R4

R3

R2

R1

0

0

0

0

0

0

0

0

0

0

C

C4(1)

3(1) C2(0) C1(0)

MUXOUT REGISTER (R12)

MUXOUT

RESERVED

READBACK

SELECT

CONTROL

BITS

M4 M3 M2

M1

OUTPUT

0

0

0

0

THREE-STATE OUTPUT

0

0

0

1

0

0

1

0

DGND

0

0

1

1

R DIVIDER OUTPUT

0

1

0

0

N DIVIDER OUTPUT

0

1

0

1

RESERVED

0

1

1

0

DIGITAL LOCK DETECT

0

1

1

1

SERIAL DATA OUTPUT

1

0

0

0

READBACK

1

0

0

1

RESERVED

1

0

1

0

CLK1 DIVIDER OUTPUT

1

0

1

1

RESERVED

1

1

0

0

RESERVED

1

1

0

1

R DIVIDER/2

1

1

1

0

N DIVIDER/2

1

1

1

1

RESERVED

R6

R5

R4

R3

R2

R1

READBACK SELECT

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

1

0

0

0

1

1

0

0

0

0

1

1

1

0

0

1

0

0

0

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

0

1

1

0

0

1

1

0

0

0

0

1

1

0

1

0

0

1

1

1

0

0

0

1

1

1

1

32 ZEROS

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

INT (16-BIT R0[19:4] VALUE)

0

1

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

1

0

0

1

1

0

1

0

1

0

0

0

1

0

1

0

1

0

1

0

1

1

0

0

1

0

1

1

1

0

1

1

0

0

0

1

0

0

1

0

1

1

0

0

1

1

1

1

0

1

0

0

0

1

1

0

1

0

1

1

1

0

1

1

0

1

1

0

1

1

1

1

1

1

0

0

0

FRAC (7-BIT R1[10:4] VALUE)

32 ZEROS

RESERVED

REVISION CODE

MR1 MASTER RESET

0

NORMAL OPERATION

RESETS ALL REGISTERS

1

L1

LE SEL

0

LE FROM PIN

LE SYNCHRONIZED WITH

RISING EDGE OF

R DIVIDER OUTPUT

1

LL

DLD AND MUXOUT LEVEL

0

1.8V LOGIC HIGH

3.3V LOGIC HIGH

1

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

Figure 35. Register 12 (R12) Map