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ADF41513 Datasheet(PDF) 18 Page - Analog Devices

Part # ADF41513
Description  26.5 GHz, Integer N/Fractional-N, PLL Synthesizer
PDF  30 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF41513 Datasheet(HTML) 18 Page - Analog Devices

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ADF41513
Data Sheet
Rev. 0 | Page 18 of 30
REGISTER 2 (R2) MAP
Phase Adjust
Set Register 2, Bit 31 to 1 to enable phase adjust. Phase adjust
increases the phase of the output relative to the current phase.
The phase change occurs after a write to Register 0.
Phase Shift = (Phase Value × 360°)/212
(5)
Phase Value
Register 2, Bits[15:4] set the phase value for phase adjust. For
example, setting the phase value = 512 increases the output
phase by 45°.
If phase adjust is not used, set the phase value to 0.
REGISTER 3 (R3) MAP
FRAC2
Register 3, Bits[27:4] set the FRAC2 value. See the N Divider
and R Counter section for more information. When using a
fixed modulus, FRAC2 is ignored.
PHASE REGISTER (R2)
DBB
CONTROL
BITS
12-BIT PHASE VALUE (PHASE)
RESERVED
PA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
P12
P11
...
P2
P1
PHASE VALUE
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
4,092
1
1
...
0
1
4,093
1
1
...
1
0
4,094
1
1
...
1
1
4,095
PHASE ADJUST
PA1
0
DISABLED
1
ENABLED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6
DB5 DB4
DB3 DB2
DB1 DB0
C3(0)
C4(0)
C2(1) C1(0)
Figure 25. Register 2 (R2) Map
FRAC2 REGISTER (R3)
DBB
CONTROL
BITS
24-BIT FRAC2 VALUE (FRAC2)
0
0
0
F1
F2
F3
F4
F5
F6
F8
F7
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
0
)
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
F24
F23
...
F2
F1
FRAC2 WORD
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
16,777,212
1
1
...
0
1
16,777,213
1
1
...
1
0
16,777,214
1
1
...
1
1
16,777,215
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6 DB5
DB4
DB3 DB2
DB1 DB0
C3(0)
C4(0)
C2(1) C1(1)
Figure 26. Register 3 (R3) Map



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