TMS320DM643 datasheet(50/160 Pages) TI

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3.1.2

Device Configuration at Device Reset

3.2

Configurations After Reset

3.2.1

Peripheral Selection After Device Reset

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 3-3 describes the DM643 device configuration pins, which are set up via external pullup/pulldown

resistors through the specified EMIFA address bus pins (AEA[22:19]), and the TOUT1/LENDIAN, and the

HD5 pins (all of which are latched during device reset).

Table 3-3. DM643 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], HD5, and MAC_EN)

CONFIGURATION

NO.

FUNCTIONAL DESCRIPTION

Device Endian mode (LEND)

TOUT1/LENDIAN

0 - System operates in Big Endian mode

1 - System operates in Little Endian mode (default)

Bootmode [1:0]

00 - No boot (default mode)

[U23,

AEA[22:21]

01 - HPI boot

V24]

10 - Reserved

11 - EMIFA boot

EMIFA input clock select

Clock mode select for EMIFA (AECLKIN_SEL[1:0])

[V25,

00 - AECLKIN (default mode)

AEA[20:19]

V26]

01 - CPU/4 Clock Rate

10 - CPU/6 Clock Rate

11 - Reserved

HPI peripheral bus width (HPI_WIDTH)

0 - HPI operates as an HPI16.

(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in

HD5

the Hi-Z state.)

1 - HPI operates as an HPI32.

(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)

(Also see the TOUT0/MAC_EN functional description in this table)

Peripheral Selection

TOUT0/MAC_EN

0 - EMAC and MDIO disabled; HPI16 enabled (default mode) [HPI32, if HD5 = 1; HPI16 if HD5 = 0]

1 - EMAC and MDIO enabled; HPI16 enabled, if HD5 = 0; HPI32 disabled, if HD5 = 1

Video Ports, McBSP0, McASP0 and I2C0

The DM643 device has designated registers for peripheral configuration (PERCFG), device status

(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration

module and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these

registers via the CFGBUS.

The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the

Video Ports (VP1 and VP2) McBSP0, McASP0, and I2C0 peripherals. For more detailed information on

the PERCFG register control bits, see Figure 3-1 and Table 3-4.

Device Configurations

TMS320DM643 Datasheet(PDF) 50 Page - Texas Instruments

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