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TMS320DM643 Datasheet(PDF) 83 Page - Texas Instruments

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Part # TMS320DM643
Description  Video/Imaging Fixed-Point Digital Signal Processo
PDF  160 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM643 Datasheet(HTML) 83 Page - Texas Instruments

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CLKOUT6
1
2
3
3
AECLKIN
2
3
4
4
5
1
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
Table 5-16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6
(1) (2) (3)
(see Figure 5-13)
–500
–600
NO.
PARAMETER
UNIT
CLKMODE = x1, x6, x12
MIN
MAX
1
tw(CKO6H)
Pulse duration, CLKOUT6 high
3P – 0.7
3P + 0.7
ns
2
tw(CKO6L)
Pulse duration, CLKOUT6 low
3P – 0.7
3P + 0.7
ns
3
tt(CKO6)
Transition time, CLKOUT6
1
ns
(1)
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2)
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
(3)
P = 1/CPU clock frequency in nanoseconds (ns)
Figure 5-13. CLKOUT6 Timing
Table 5-17. Timing Requirements for AECLKIN for EMIFA
(1) (2) (3) (see Figure 5-14)
–500
–600
NO.
UNIT
MIN
MAX
1
tc(EKI)
Cycle time, AECLKIN
6(4)
16P
ns
2
tw(EKIH)
Pulse duration, AECLKIN high
2.7
ns
3
tw(EKIL)
Pulse duration, AECLKIN low
2.7
ns
4
tt(EKI)
Transition time, AECLKIN
3
ns
5
tJ(EKI)
Period jitter, AECLKIN
0.02E
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
(2)
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3)
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
(4)
Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600
devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 devices, 100-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met.
Figure 5-14. AECLKIN Timing for EMIFA
DM643 Peripheral Information and Electrical Specifications
83



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