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TMS320DM643 Datasheet(PDF) 29 Page - Texas Instruments |
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TMS320DM643 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 160 page ![]() www.ti.com TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005 Table 2-4. Terminal Functions (continued) SIGNAL IPD/ TYPE(1) DESCRIPTION IPU(2) NAME NO. GP0[15] G3 GP0[14] C1 GP0[13] G4 General-purpose input/output GP0[15:9] pins (I/O/Z). GP0[12] H4 Note: By default, no function is enabled upon reset. To configure these pins, see I/O/Z the Device Configuration section of this data sheet. GP0[11] F1 GP0[10] J2 GP0[9] K3 GP0[3] L5 IPD GP0 3 pin (I/O/Z) General-purpose 0 pin (GP0[0]) (I/O/Z) [default] This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0] (output only) pin or output as a general-purpose interrupt (GP0INT) signal GP0[0] M5 I/O/Z IPD (output only). Note: This pin must remain low during device reset. VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter VDAC/GP0[8](3) AD1 I/O/Z IPD (VDAC) output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be CLKOUT6/GP0[2](3) C6 I/O/Z IPD programmed as a GP0 2 pin (I/O/Z). Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be CLKOUT4/GP0[1](3) D6 I/O/Z IPD programmed as a GP0 1 pin (I/O/Z). HOST-PORT INTERFACE (HPI) or EMAC HINT N4 O/Z Host interrupt from DSP to host (O). HCNTL1 P1 I Host control – selects between control, address, or data registers (I). HCNTL0 R3 I Host control – selects between control, address, or data registers (I). Host half-word select – first or second half-word (not necessarily high or low HHWIL N3 I order). [For HPI16 bus width selection only] (I). HR/W M1 I Host read or write select (I). HAS P3 I Host address strobe (I) Host chip select (I) HCS R1 I Host data strobe 1 (I) HDS1 R2 I Host data strobe 2 (I) Note: If unused, the following HPI control signals should be externally pulled HDS2 T2 I high. HRDY N1 O/Z Host ready from DSP to host (O) Device Overview 29 |
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