22

PC8240

2149A–HIREL–05/02

Output AC Timing

Specification

Table 11 provides the processor bus AC timing specifications for the PC8240. See Fig-

ure10on page21and Figure11on page21.

andLVdd= 3.3V ±5%

Notes:

1. All memory and related interface output signal specifications are specified from the V

ory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as

PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on

every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21.

2. All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or 0.615*OVdd of the signal

in question for 3.3V PCI signaling levels. See Figure 11 on page 21.

3. All output timings assume a purely resistive 50

Ω load (See Figure 13 on page 23). Output timings are measured at the pin;

time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

4. PCI Bussed signals are composed of the following signals: LOCK, IRDY,C/BE[0 – 3], PAR, TRDY,FRAME,STOP,

DEVSEL, PERR, SERR, AD[0 – 31], REQ[4–0], GNT[4 – 0], IDSEL,INTA.

5. PCI hold times can be varied, see “PCI Signal Output Hold Timing” on page 23 for information on programmable PCI output

hold times. The values shown for item 13a are for PCI compliance.

6. These specifications are for the default driver strengths indicated in Table 7 on page 17.

Table 11. Output AC Timing Specifications

Num

Characteristics

(3)(6)

Min

Max

Unit

Notes

12a

PCI_SYNC_IN to Output Valid, 66 MHz PCI, with MCP pulled-down

to logic 0 state. See Figure 14.

–6.0

ns

(2)(4)

PCI_SYNC_IN to Output Valid, 33 MHz PCI, with MCP in the default

logic 1 state. See Figure 14.

–8.0

ns

(2)(4)

12b1

SDRAM_SYNC_IN to Output Valid

(For Memory Control and Data Signals accessing DRAM in Flow

Through Mode)

–7.0

ns

(1)

12b2

SDRAM_SYNC_IN to Output Valid

(For Memory Control and Data Signals accessing DRAM in

Registered

Mode)

–TBD

ns

(1)

12b3

SDRAM_SYNC_IN to Output Valid

(For Memory Control and Data Signals accessing non-DRAM)

–TBD

ns

(1)

12c

SDRAM_SYNC_IN to Output Valid (For All Others)

–

7.0

ns

(1)

12d

SDRAM_SYNC_IN to Output Valid (For Two-wire Interface)

–

TBD

ns

(1)

13a

Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic 0

states. See Table 12.

0.5

–

ns

(2)(4)(5)

Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and

CKE pulled-down to logic 0 state. See Table 12.

2.0

–

ns

(2)(4)(5)

13b

Output Hold (For All Others)

0

–

ns

(1)

14a

PCI_SYNC_IN to Output High Impedance (For PCI)

–

TBD

ns

(2)(4)

14b

SDRAM_SYNC_IN to Output High Impedance (For All Others)

–

TBD

ns

(1)