PC8240 datasheet(29/42 Pages) ATMEL

29 / 42 page

PC8240

2149A–HIREL–05/02

Figure 19. EPIC Serial Interrupt Mode Output Timing Diagram

Figure 20. EPIC Serial Interrupt Mode Input Timing Diagram

IEEE 1149.1 (JTAG) AC Timing

Specifications

Table 17 provides the JTAG AC timing specifications for the PC8240 while in the JTAG

operating mode.

At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ±5%

andLVdd= 3.3V ±5%

S_CLK

S_RST

S_FRAME

sys_logic_clk3

S_CLK

S_INT

Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)

Num

Characteristics

(4)

Min

Max

Unit

Notes

TCK Frequency of Operation

MHz

TCK Cycle Time

–

TCK Clock Pulse Width Measured at 1.5V

–

TCK Rise and Fall Times

TRST_ Setup Time to TCK Falling Edge

–

(1)

5TRST_ Assert Time

–

Input Data Setup Time

–

(2)

Input Data Hold Time

–

(2)

TCK to Output Data Valid

(3)

TCK to Output High Impedance

(3)

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