28

PC8240

2149A–HIREL–05/02

Figure 18. Two-wire Interface Timing Diagram IV (Qualified signal)

EPIC Serial Interrupt Mode AC

Timing Specifications

Table 16 provides the EPIC serial interrupt mode AC timing specifications for the

PC8240.

At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%

and LVdd = 3.3V ± 5%

Notes:

1. See the PC8240 User’s Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency

programming.

2. S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and S_CLK

and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the Motorola’s PC8240 User’s

Manual for a complete description of the functional relationships between these signals.

3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;

sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is

implemented and the DLL is locked. See Motorola’s PC8240 User’s Manual for a complete clocking description.

SCL/SDArealtime

VM

SCL/SDAqualified

VM

Note 1: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.

Table 16. EPIC Serial Interrupt Mode AC Timing Specifications

Num

Characteristics

Min

Max

Unit

Notes

1

S_CLK Frequency

1/14 SDRAM_SYNC_IN

1/2 SDRAM_SYNC_IN

MHz

(1)

2

S_CLK Duty Cycle

40

60

%

3

S_CLK Output Valid Time

–

TBD = x

nS

4

Output Hold Time

0

–

nS

5S_FRAME, S_RST Output Valid

Time

–

1 sys_logic_clk period + x

nS

(2)

6

S_INT Input Setup Time to S_CLK

1 sys_logic_clk period + TBD

–

nS

(2)

7

S_INT Inputs Invalid (Hold Time) to

S_CLK

–0

nS

(2)