-48V Hot-Swap Controllers

_______________________________________________________________________________________

7

Timing Diagrams (continued)

DRAIN

PWRGD

PWRGD

DRAIN

1V

1.4V

1.4V

1V

Figure 6a. DRAIN to PWRGD/PWRGD Timing

GATE

PWRGD

GATE

PWRGD

1.4V

1.4V

1V

1V

Figure 6b. GATE to PWRGD/PWRGD Timing

LOGIC

GATE

DRIVER

500

µs

DELAY

UVLO

REFERENCE

GENERATOR

REF

REF

50mV

UV

OV

SENSE

GATE

DRAIN

PWRGD

PWRGD

MAX5949A

MAX5949B

OUTPUT DRIVE

Block Diagram