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HD64F2145 Datasheet(PDF) 362 Page - Renesas Technology Corp

Part # HD64F2145
Description  Hitachi 16-Bit Single-Chip Microcomputer
PDF  829 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2145 Datasheet(HTML) 362 Page - Renesas Technology Corp

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Rev. 2.0, 08/02, page 322 of 788
Mode
IVI Signal
IVO Signal
Meaning of IVO Signal
IVI signal (without fall
modification or IHI
synchronization)
VSYNCI input (vertical synchronization signal)
is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VSYNCI input (vertical
synchronization signal) is synchronized with
HSYNCI input (horizontal synchronization
signal)
IVI signal (with fall
modification, without IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified and signal is synchronized with
HSYNCI input (horizontal synchronization
signal) before output
Separate
mode
VSYNCI
input
IVG signal
Internal synchronization signal is output
13.4.9
CBLANK Output
Using the signals generated/selected with timer connection, it is possible to generate a waveform
based on the composite synchronization signal (blanking waveform).
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the
IVO signal.
The logic of CBLANK output waveform generation is shown in figure 13.9.
Reset
Set
CBLANK signal
(positive)
HFBACKI input (positive)
VFBACKI input (positive)
IVO signal (positive)
Q
Falling edge sensing
Rising edge sensing
Figure 13.9 CBLANK Output Waveform Generation



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