HD64F2145 datasheet(366/829 Pages) RENESAS

366 / 829 page

Rev. 2.0, 08/02, page 326 of 788

WOVI0

(Interrupt request signal)

Internal NMI

(Interrupt request signal*2)

signal*1

Internal reset signal*1

TCNT_0

TCSR_0

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Internal clock

Overflow

Interrupt

control

Reset

control

WOVI1

(Interrupt request signal)

Internal reset signal*1

signal*1

TCNT_1

TCSR_1

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Clock

selection

Internal clock

Bus

interface

Module bus

TCSR_0

: Timer control/status register_0

TCNT_0

: Timer counter_0

TCSR_1

: Timer control/status register_1

TCNT_1

: Timer counter_1

Notes: 1. The

signal outputs the low level signal when the internal reset signal is

generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal

first resets the WDT in which the overflow has occurred first.

2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.

The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from

that from WDT_1.

WDT_1

Legend

Internal NMI

(Interrupt request signal*2)

øSUB/2

øSUB/4

øSUB/8

øSUB/16

øSUB/32

øSUB/64

øSUB/128

øSUB/256

Overflow

Interrupt

control

Reset

control

Clock

selection

Bus

interface

Module bus

WDT_0

Figure 14.1 Block Diagram of WDT

HD64F2145 Datasheet(PDF) 366 Page - Renesas Technology Corp

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