HD64F2145 datasheet(368/829 Pages) RENESAS

368 / 829 page

Rev. 2.0, 08/02, page 328 of 788

14.3.2

Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode.

• TCSR_0

Bit

Bit Name

Initial

Value

R/W

Description

7OVF

R/(W)*

Overflow Flag

Indicates that TCNT has overflowed (changes from H’FF

to H’00).

[Setting condition]

When TCNT overflows (changes from H’FF to H’00)

However, when internal reset request generation is

selected in watchdog timer mode, OVF is cleared

automatically by the internal reset.

[Clearing conditions]

• When TCSR is read when OVF = 1*2, then 0 is

written to OVF

• When 0 is written to TME

6WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog timer or

interval timer.

0: Interval timer mode

1: Watchdog timer mode

TME

R/W

Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and is

initialized to H'00.

4—

R/(W)

Reserved

The initial value should not be modified.

RST/

10, 0

R/W

Reset or NMI

Selects to request an internal reset or an NMI interrupt

when TCNT has overflowed.

0: An NMI interrupt is requested

1: An internal reset is requested

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