HD64F2145 datasheet(433/829 Pages) RENESAS

433 / 829 page

Rev. 2.0, 08/02, page 393 of 788

Section 16 I

2C Bus Interface (IIC) (Optional)

The I

2C bus interface is provided as an optional function. Note the following point when using this

optional function.

• Although the product type name is identical, please contact Hitachi before using this optional

function on an F-ZTAT version product.

This LSI has a two-channel I

2C bus interface. The I2C bus interface conforms to and provides a

subset of the Philips I

2C bus (inter-IC bus) interface functions. The register configuration that

controls the I

2C bus differs partly from the Philips configuration, however.

16.1

Features

• Selection of addressing format or non-addressing format

 I2C bus format: addressing format with an acknowledge bit, for master/slave operation

 Clocked synchronous serial format: non-addressing format without an acknowledge bit, for

master operation only

 Formatless (for IIC_0 only): non-addressing format with a clock pin dedicated for

formatless; for slave operation only

• Conforms to Philips I2C bus interface (I2C bus format)

• Two ways of setting slave address (I2C bus format)

• Start and stop conditions generated automatically in master mode (I2C bus format)

• Selection of the acknowledge output level in reception (I2C bus format)

• Automatic loading of an acknowledge bit in transmission (I2C bus format)

• Wait function in master mode (I2C bus format)

 A wait can be inserted by driving the SCL pin low after data transfer, excluding

acknowledgement.

 The wait can be cleared by clearing the interrupt flag.

• Wait function (I2C bus format)

 A wait request can be generated by driving the SCL pin low after data transfer.

 The wait request is cleared when the next transfer becomes possible.

• Interrupt sources

 Data transfer end (including when a transition to transmit mode with I2C bus format occurs,

when ICDR data is transferred, or during a wait state)

 Address match: When any slave address matches or the general call address is received in

slave receive mode with I

2C bus format (including address reception after loss of master

arbitration)

 Start condition detection (in master mode)

 Stop condition detection (in slave mode)

IFIIC60A_000020020700

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