HD64F2145 datasheet(437/829 Pages) RENESAS

437 / 829 page

Rev. 2.0, 08/02, page 397 of 788

16.3

The I

2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR

and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit

in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit

is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer

to section 3.2.3, Serial Timer Control Register (STCR).

• I2C bus control register (ICCR)

• I2C bus status register (ICSR)

• I2C bus data register (ICDR)

• I2C bus mode register (ICMR)

• Slave address register (SAR)

• Second slave address register (SARX)

• I2C bus extended control register (ICXR)

• DDC switch register (DDCSWR) (for IIC_0 only)

16.3.1

2C Bus Data Register (ICDR)

ICDR is an 8-bit readable/writable register that is used as a transmit data register when

transmitting and a receive data register when receiving. ICDR is internally divided into a shift

these three registers are performed automatically in accordance with changes in the bus state, and

they affect the status of internal flags such as ICDRE and ICDRF.

In master transmit mode with the I

2C bus format, writing transmit data to ICDR should be

performed after start condition detection. When the start condition is detected, previous write data

is ignored. In slave transmit mode, writing should be performed after the slave addresses match

and the TRS bit is automatically changed to 1.

If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag is

0) after successful transmission/reception of one frame of data using ICDRS, data is transferred

automatically from ICDRT to ICDRS.

If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data

is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data

using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is

transferred automatically from ICDRT to ICDRS by writing to ICDR. If I

2C is in receive mode

(TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to

ICDR in receive mode.

Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.

HD64F2145 Datasheet(PDF) 437 Page - Renesas Technology Corp