HD64F2145 datasheet(438/829 Pages) RENESAS

438 / 829 page

Rev. 2.0, 08/02, page 398 of 788

If I

2C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is

transferred automatically from ICDRS to ICDRR, following reception of one frame of data using

ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically

from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from

ICDRS to ICDRR. Always set I

2C to receive mode before reading from ICDR.

If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data

and receive data are stored differently. Transmit data should be written justified toward the MSB

side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should

be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.

ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value

of ICDR is undefined.

16.3.2

Slave Address Register (SAR)

SAR sets the slave address and selects the communication format. If the LSI is in slave mode with

the I

2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the

upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device

specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to

Bit

Bit Name

Initial Value R/W

Description

SVA6

SVA5

SVA4

SVA3

SVA2

SVA1

SVA0

R/W

Slave Address 6 to 0

Set a slave address.

0FS

R/W

Format Select

Selects the communication format together with the FSX bit

in SARX and the SW bit in DDCSWR. Refer to table 16.2.

This bit should be set to 0 when general call address

recognition is performed.

HD64F2145 Datasheet(PDF) 438 Page - Renesas Technology Corp

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