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HD64F2145 Datasheet(PDF) 435 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 435 Page - Renesas Technology Corp |
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435 / 829 page  Rev. 2.0, 08/02, page 395 of 788 Figure 16.1 shows a block diagram of the I 2C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Since I 2C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 28, Electrical Characteristics. ø SCL PS Noise canceler Bus state decision circuit Arbitration decision circuit Output data control circuit ICCR Clock control ICXR ICMR ICSR ICDRS Address comparator SAR, SARX SDA Noise canceler Interrupt generator Interrupt request ICDRR ICDRT Formatless dedicated clock (IIC_0 only) Legend: ICCR: ICMR: ICSR: ICDR: ICXR: SAR: SARX: PS: I2C bus control register I2C bus mode register I2C bus status register I2C bus data register I2C bus extended control register Slave address register Slave address register X Prescaler Figure 16.1 Block Diagram of I 2C Bus Interface |
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