AD9878BSTZ datasheet(16/36 Pages) AD

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AD9878

Rev. A | Page 16 of 36

Bits [6:0]: Clamp Level Control Value

The 7-bit clamp-level control value is used to set an offset to the

automatic clamp-level control loop. The actual ADC output has a

clamp-level offset equal to 16 times the clamp level control value.

( )16

Value

Control

Level

Clamp

Offset

Level

Clamp

The default value for the clamp-level control value is 0x20. This

results in an ADC output clamp-level offset of 512 LSBs. The

valid programming range for the clamp-level control value is

0x16 to 0x127.

Bit 7: Video Input Enable

This bit enables the video input. In default with Bit 7 = 0, both

IF12 ADCs are connected to IF inputs. If the video input is

enabled by setting bit 7 = 1, the video input will be connected to

the IF12 ADC selected by REG 0x03, Bit 6.

Bit 0: Send ADC12B Data Only

When this bit is set high, the device enters a nonmultiplexed

mode, and only the data from the ADC12B is sent to the

IF[11:0] digital output port.

Bit 1: Send ADC12A Data Only

When this bit is set high, the device enters a nonmultiplexed

mode, and only the data from the ADC12A is sent to the

IF[11:0] digital output port.

If both the send ADC12B data only and send ADC12A data

only register bits are set high, the device sends both ADC12A

and ADC12B data in the default multiplexed mode.

Bit 3: Power Down ADC10 Voltage Reference

Active high powers down the voltage reference circuit for

the ADC10.

Bit 4: Power Down RxSYNC Generator

Setting this bit to 1 powers down the 10-bit ADC’s sampling

clock and makes the RxSYNC output pin stay low. It can be

used for additional power saving on top of the power-down

selections in Register 0x02.

Bit 5: Rx PORT Fast Edge Rate

Setting this bit to 1 increases the output drive strength of all digital

output pins, except MCLK, REFCLK, SIGDELT, and

FLAG[2:1]. These pins always have high output drive capability.

Bit 7: ADC Clocked Directly from OSCIN

When set high, the ADC sampling clock is derived directly from

the input clock at OSCIN. In this mode, the clock supplied to the

OSCIN pin should originate from an external crystal or low jitter

crystal oscillator. When this bit is low, the ADC sampling clock

is derived from the internal PLL and the frequency of the clock

is equal to fOSCIN × M/8.

Bits [3:0]: Version

The die version of the chip can be read from this register.

LSBs

This register accommodates the 2 LSBs for each frequency tuning

word (FTW). See the Registers 0x10 Through 0x17—

Burst Parameter section.

This register allows the user to program the DAC gain if the

Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.

Table 5. DAC Gain Control

Bits [3:0]

DAC Gain (dB)

0000

0.0 (default)

0001

0.5

0010

1.0

0011

1.5

…

1110

7.0

1111

7.5

Bit 0: Single Tone Tx Mode

Active high configures the AD9878 for single-tone applications

(e.g., FSK). The AD9878 supplies a single frequency output, as

determined by the FTW selected by the active profile. In this

mode, the TxIQ input data pins are ignored, but should be tied

to a valid logic voltage level. Default value is 0x00 (inactive).

Bit 1: Spectral Inversion Tx

When set to 1, inverted modulation is performed:

( )

[

sin

cos

OUT

MODULATOR

Default is Logic 0, noninverted modulation:

()

( )

[

sin

cos

OUT

MODULATOR

−

Bit 2: Bypass Inv Sinc Tx Filter

Active high configures the AD9878 to bypass the sin(x)/x com-

pensation filter. Default value is 0x00 (inverse sinc filter enabled).

Bit 3: CA Interface Mode Select

This bit changes the format of the AD9878 3-wire CA interface to

a format in which the AD9878 digitally interfaces to external

variable gain amplifiers. This is accomplished by changing

the interpretation of the bits in Register 0x13, Register 0x17,

Control section for more detail.

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