HMA41GR7AFR4N datasheet(60/79 Pages) HYNIX

60 / 79 page

Rev. 1.0 / Mar.2016

IDD6R

Self-Refresh Current: Reduced Temperature Range

TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;

External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,

Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:

Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;

ODT Signal: MID-LEVEL

IPP6R

Self Refresh IPP Current: Reduced Temperature Range

Same condition with IDD6R

IDD6A

Auto Self-Refresh Current

TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;

CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh

operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL

IPP6A

Auto Self-Refresh IPP Current

Same condition with IDD6A

IDD7

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:

CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address

Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between

one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times

interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and

RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10

IPP7

Operating Bank Interleave Read IPP Current

Same condition with IDD7

IDD8

Maximum Power Down Current

TBD

IPP8

Maximum Power Down IPP Current

Same condition with IDD8

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