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SAM2695 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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SAM2695 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 44 page ![]() 3 SAM2695 Miscellaneous group Pin name Pin # Type Description RST/PD/ 38 IN-5VT Master reset and Power down. Schmitt trigger input. RST/PD/ should be held low during at least 10ms after power is applied. On the rising edge of RST/PD/ the chip enters its initialization routine. When RST/PD/ is low, Power-down is active: 8-bit port data lines are High-Z. IRQ is set to 0. The PLL is stopped and supply voltage is removed from analog and digital core. To exit from power down, RST/PD/ must be set to VD33. X1-X2 39, 40 - 9.6 MHz or 12 MHz crystal connection. An external clock can also be used on X1. XDIV 47 IN System clock divider. - When grounded, it allows using 9.6MHz crystal - When connected to VD33, it allows using 12MHz crystal OUTVC12 34 PWR 3.3V to 1.2 V regulator output. The built-in regulator gives 1.2V for internal use only (core supply). 4.7µF or 10µF Decoupling capacitor must be connected between OUTVC12 and GND. TEST 37 IN Test pin with a built-in pull-down. It should be grounded or left open for normal operation. NC 17, 19, 21-23; 43, 44 - Not connected pins. 1-2- PINOUT BY PIN # - 48-lead QFN Package Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name 1 AOUTL 13 GND 25 GND 37 TEST 2 AOUTR 14 CS/ 26 D1 38 RST/PD/ 3 VCMHPOUT 15 RD/ 27 D2 39 X1 4 AGND 16 MIDI_IN 28 D3 40 X2 5 VCM 17 NC 29 D4 41 VD33 6 VA33 18 GND 30 D5 42 IRQ 7 MICIN 19 NC 31 VD33 43 NC 8 VD33 20 VD33 32 D6 44 NC 9 GND 21 NC 33 D7 45 GND 10 A0 22 NC 34 OUTVC12 46 VD33 11 VD33 23 NC 35 VD33 47 XDIV 12 WR/ 24 D0 36 GND 48 GND |
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