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SAM5808B Datasheet(PDF) 80 Page - List of Unclassifed Manufacturers

Part # SAM5808B
Description  AUDIO & MUSIC MULTI-DSP PROCESSOR
PDF  83 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SAM5808B Datasheet(HTML) 80 Page - List of Unclassifed Manufacturers

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SAM5808B
SAM5808B.pdf
– Rev 14/05/2018
80
© 2015-2018 Dream S.A.S., France
12.4. SDR SDRAM
For SDRAM following layout rules should be applied:
 4 layer PCB is needed for SDR SDRAM. Layer 1 = Signal + Ground plane, Layer 2 =
Ground plane, Layer 3 = Signal + Power Supply Plane, Layer 4 = Signal + Ground plane
 If 4 SDRAM memory devices, it is recommended to implement 2 devices on each side of
the PCB.
 All DRDQ15-DRDQ0, DRDS0-DRDS1, DRDM0-DRDM1 should be routed together and
should have same length, considering all the SDRAM devices. It means that each DRDQx
signal should have the same length from its SAM5808B DRDQx pin to each of the DRDQx
pin of each SDRAM device. It also means that all the DRDQx and DRDMx signals should
have the same length.
 All DRDA13-DRDA0, DRDBA1-DRDBA0 should be routed together and should have the
same length, considering one SDRAM device. It means that all the DRDAx/DRDBAx
signals should have a same length L1 from SAM5808B to the first SDRAM device and a
same length L2 from SAM5808B to the second SDRAM device... Tolerance should be
lower than +/-2mm.
 DRRAS/, DRCAS/, DRWE/, DRCKE should be routed together and should have the same
length.
 SDRAM systems have only a single-ended clock (DRCK), so the important trace-matching
relationship is not to a second differential clock trace but instead to the other groups. Match
clock traces to data group traces within ±12mm. If multiple clocks are transmitted from the
controller to components, all clock traces should be equivalent to within ±0.5mm. Matching
trace lengths to this level of accuracy helps minimize skew.
It is also needed to match clock traces to each signal trace in the address and command
groups to within ±10mm. If clock traces cannot be matched to the trace lengths of these
groups within 10mm, then all clock trace lengths must be increased as a group. The
longest-to-shortest trace-
length difference must be ≤20mm, so both longest and shortest
traces determine how much length must be added to all clock lines.



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