DSC6311ME2AA-T datasheet(4/28 Pages) MICROCHIP

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DSC63XX

DS20005808A-page 4

 2017 Microchip Technology Inc.

Output Transition Time

Rise Time/Fall Time

tRX/tFX

—1

1.5

DSC63x2

High Drive,

20% to 80%

CL = 15 pF

VDD = 1.8V

—0.5

1.0

VDD = 2.5V/3.3V

tRY/tFY

—1.2

2.0

DSC63x1

Std Drive,

20% to 80%

CL = 10 pF

VDD = 1.8V

—1

1.6

VDD = 2.5V/3.3V

Frequency

1—

100

MHz

—

Output Duty Cycle

SYM

—

Period Jitter, RMS

JPER

—14

—

psRMS

FOUT =

27 MHz

VDD = 1.8V

—11

—

VDD = 2.5V/3.3V

Cycle-to-Cycle Jitter

(peak)

JCy–Cy

—75

—

FOUT =

27 MHz

VDD = 1.8V

—53

—

VDD = 2.5V/3.3V

Spread Spectrum

Modulation Frequency

fSS

—33

—

kHz

—

Spread Spectrum

Modulation and Type

—

±0.25

—

Center Spread

—±0.5

—

—±1

—

—±1.5

—

—±2

—

—±2.5

—

–0.25

—

Down Spread

—–0.5

—

—–1

—

—–1.5

—

—–2

—

—–3

—

DSC63XX ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to 85°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1: Pin 4 VDD should be filtered with 0.1 µf capacitor.

2: Not including current through pull-up resistor on EN pin (if configured). Higher standby current seen at

>3.3V VDD.

3: Includes frequency variations due to initial tolerance, temperature, and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to one period of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

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