Specifications

Product specifications and descriptions in this document are subject to change without notice.

All specifications are guaranteed unless noted otherwise. All specifications apply to all models unless noted otherwise.

Vertical system

Rise Time / Bandwidth

Determined by the sampling modules used

Vertical Resolution

16 bits over the sampling modules' dynamic range

Electrical Resolution: <20 μV LSB (for 1 V full range)

Optical resolution depends on the dynamic range of the optical module – ranges from <20 nW for the 80C07B (1 mW full range) to

<0.6 μW for the 80C10C (30 mW full range)

Horizontal system

Main and Magnification View Time

Bases, Horizontal Scale

100 fs/div to 1 ms/div, in 1-2-5 sequence or 100 fs increments

Time Interval Accuracy

Trigger Direct (Front Panel)

Input

Horizontal scale >20 ps/div, right-most point of measurement interval <150 ns; Mean Accuracy: 0.1% of interval, STDEV: ≤1 ps

Horizontal scale ≤20 ps/div, right-most point of measurement interval <150 ns; Mean Accuracy: 1 ps + 0.5% of interval

Clock Input/Prescale Trigger

(Front Panel), Eye or Pattern

Mode

Mean accuracy determined by clock input accuracy STDEV: <0.7 ps (max); <0.1 ps (typical)

Clock Input/Prescale Trigger

(Front Panel), Other Mode

Horizontal scale >20 ps/div, right-most point of measurement interval <150 ns; Mean Accuracy: 0.1% of interval, STDEV: ≤3 ps

Horizontal scale ≤20 ps/div, right-most point of measurement interval <150 ns; Mean Accuracy: 1 ps + 0.5% of interval

TDR Clock Trigger (Lock to

External 10 MHz Clock)

Horizontal scale >20 ps/div, right-most point of measurement interval <150 ns; Mean Accuracy: 0.01% of interval, STDEV: ≤1 ps

(0.1 ps typical)

Random Phase Corrected

Mode (Clock Input to 82A04B)

Maximum timing deviation 0.1% of phase reference signal period, typical, relative to phase reference signal

For more information on phase reference modes of operation, see the “Phase Reference Module for the DSA8300 Sampling

Oscilloscope” datasheet.

Triggered Phase Corrected

Mode (Clock Input to 82A04B)

Maximum timing deviation relative to phase reference signal:

>40 ns after trigger event: 0.2% of phase reference signal period, typical

≤40 ns after trigger event: 0.4% of phase reference signal period, typical

Horizontal Deskew Range

Available

SW: –500 ps to +100 ns on any individual channel in 100 fs increments, some limitations apply to software deskew TDR and

sampling modules. Note that SW deskew implies acquiring another waveform, at a different horizontal position; a throughput

penalty exists.

Mainframe channel delay (HW deskew):

Sample mode:

80E11 and 80E11x1: ±35 ps

80E07B, 80E08B, 80E09B, and 80E10B: ±150 ps

80C17, 80C18: +/- 65 ps

TDR mode:

80E08B and 80E10B: ±200 ps

DSA8300 Digital Serial Analyzer Sampling Oscilloscope

www.tek.com 5