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LPC47M112 Datasheet(PDF) 73 Page - SMSC Corporation |
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LPC47M112 Datasheet(HTML) 73 Page - SMSC Corporation |
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73 / 208 page ![]() Enhanced Super I/O Controller with LPC Interface Datasheet SMSC DS – LPC47M112 Page 73 Rev. 02/02/2005 DESIRED BAUD RATE DIVISOR USED TO GENERATE 16X CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 1 HIGH SPEED BIT 2 1800 64 - X 2000 58 0.005 X 2400 48 - X 3600 32 - X 4800 24 - X 7200 16 - X 9600 12 - X 19200 6 - X 38400 3 0.030 X 57600 2 0.16 X 115200 1 0.16 X 230400 32770 0.16 1 460800 32769 0.16 1 Note 1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%. Note 2: The High Speed bit is located in the Device Configuration Space. |
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