LPC47M112 datasheet(87/208 Pages) SMSC

87 / 208 page

Enhanced Super I/O Controller with LPC Interface

Datasheet

SMSC DS – LPC47M112

Page 87

Rev. 02/02/2005

The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization

by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and

output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during

which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read.

An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the

deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP

mode.

EPP DATA PORT 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a

description of operation. This register is only available in EPP mode.

EPP DATA PORT 2

ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a

description of operation. This register is only available in EPP mode.

EPP DATA PORT 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a

description of operation. This register is only available in EPP mode.

EPP 1.9 OPERATION

When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also

available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-

directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is

controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to

prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT

being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is

indicated in Status bit 0.

During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write

mode and the nWRITE signal to always be asserted.

Software Constraints

Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or

05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write,

the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the

parallel bus, no error is indicated.

EPP 1.9 Write

The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The

chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The

write cycle can complete under the following circumstances:

If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can

complete when nWAIT goes inactive high.

If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the

state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.

Write Sequence of operation

The host initiates an I/O write cycle to the selected EPP register.

If WAIT is not asserted, the chip must wait until WAIT is asserted.

The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

LPC47M112 Datasheet(PDF) 87 Page - SMSC Corporation

LPC47M112 Datasheet(HTML) 87 Page - SMSC Corporation

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