DS3254 datasheet(49/71 Pages) DALLAS

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Table 17-H. Parallel CPU Interface Timing

(VDD = 3.3V

±5%, TA = -40°C to +85°C.) (Figure 17-3 and Figure 17-4)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Setup Time for A[5:0] Valid to

CS Active (Notes 1, 2)

Setup Time for

CS Active to RD, WR, or DS Active

Delay Time from

RD or DS Active to D[7:0] Valid

Hold Time from

RD or WR or DS Inactive to CS Inactive

Delay from

CS or RD or DS Inactive to D[7:0] Invalid or Tri-

State (Note 3)

Wait Time from

WR or DS Active to Latch D[7:0]

D[7:0] Setup Time to

WR or DS Inactive

D[7:0] Hold Time from

WR or DS Inactive

A[5:0] Hold Time from

WR or RD or DS Inactive

RD, WR, or DS Inactive Time

t10

Muxed Address Valid to ALE Falling (Note 4)

t11

Muxed Address Hold Time (Note 4)

t12

ALE Pulse Width (Note 4)

t13

Setup Time for ALE High or Muxed Address Valid to

Active (Note 4)

t14

Note 1:

D[7:0] loaded with 50pF when tested as outputs.

Note 2:

If a gapped clock is applied on TCLK and local loopback is enabled, read cycle time must be extended by the length of the largest

TCLK gap.

Note 3:

Not tested during production test.

Note 4:

In nonmultiplexed bus applications (Figure 17-3), ALE should be wired high. In multiplexed bus applications (Figure 17-4), A[5:0]

should be wired to D[5:0] and the falling edge of ALE latches the address.

DS3254 Datasheet(PDF) 49 Page - Dallas Semiconductor

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