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CS4270 Datasheet(PDF) 16 Page - Cirrus Logic

Part # CS4270
Description  24-Bit, 192 kHz Stereo Audio CODEC
PDF  48 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4270 Datasheet(HTML) 16 Page - Cirrus Logic

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16
DS686A1
CS4270
DIGITAL CHARACTERISTICS
16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN
Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF)
Parameter (Note 16)
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Serial Port
Control Port
VIH
0.7xVD
0.7xVLC
-
-
-
-
V
V
Low-Level Input Voltage
Serial Port
Control Port
VIL
-
-
-
-
0.2xVD
0.2xVLC
V
V
High-Level Output Voltage at Io = 2 mA
Serial Port
Control Port
MUTEA, MUTEB
VOH
VD - 1.0
VLC - 1.0
VA - 1.0
-
-
-
-
-
-
V
V
V
Low-Level Output Voltage at Io = 2 mA
VOL
--
0.4
V
Input Leakage Current
Iin
-10
-
10
µA
Parameter
Symbol
Min
Typ
Max
Unit
Sample Rate
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
54
108
216
kHz
kHz
kHz
MCLK Specifications
MCLK Frequency
Stand-Alone Mode
(
Note 17)
Control Port Mode
fmclk
fmclk
1.024
1.024
-
-
55.296
55.296
MHz
MHz
MCLK Duty Cycle
40
50
60
ns
Master Mode
LRCK Duty Cycle
-50
-
%
SCLK Period
--
s
SCLK Duty Cycle
-50
-
%
SCLK falling to LRCK edge
tslr
-10
-
10
ns
SCLK falling to SDOUT valid
tsdo
-
-
32
ns
SDIN valid to SCLK rising setup time
tsdis
16
-
-
ns
SCLK rising to SDIN hold time
tsdih
20
-
-
ns
Slave Mode
LRCK Duty Cycle
40
50
60
%
SCLK Period
(
Note 17)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tsclkw
tsclkw
tsclkw
-
-
-
-
-
-
s
s
s
SCLK Duty Cycle
45
50
55
ns
SCLK falling to LRCK edge
tslr
-10
-
10
ns
1
64
()Fs
------------------
1
128
()Fs
---------------------
1
128
()Fs
---------------------
1
64
()Fs
------------------



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