AX58100LT datasheet(11/71 Pages) ASIX

11 / 71 page

AX58100

EtherCAT Slave Controller

Pin Name

Type

Pin No

Pin Description

P0_TXOP

PHY 0 differential Transmitted Positive signal

In the copper mode, the differential data is transmitted to the media on the

TXOP/TXON signal pair in the MDI mode.

In the fiber mode, the signal pair should be connected to the TX+/TX- pin of the

fiber transceiver.

P0_TXON

PHY 0 differential Transmitted Negative signal

P0_RXIP

PHY 0 differential Received Positive signal

In the copper mode, the differential data from the media is received on the

RXIP/RXIN signal pair in the MDI mode.

In the fiber mode, the signal pair should be connected to the RX+/RX- pin of the

fiber transceiver.

P0_RXIN

PHY 0 differential Received Negative signal

P0_SD

PHY 0 fiber mode Signal Detect

SD < 0.2V, Copper mode-

1.0V < SD < 1.8V, Fiber mode without detected signal. Generate far-end fault

SD > 2.4V, Fiber mode with detected signal

P0_ACT\

P0_FIBER

B5/4m

PHY 0 Link/Activity LED

This pin is input direction during chip reset stage used to bootstrap the mode

setting to decide the PHY 0 media mode, please refer to Section 3.1

P1_TXOP

PHY 1 differential Transmitted Positive signal

Same as PHY0 TXOP/ON description

P1_TXON

PHY 1 differential Transmitted Negative signal

P1_RXIP

PHY 1 differential Received Positive signal

Same as PHY0 RXIP/IN description

P1_RXIN

PHY 1 differential Received Negative signal

P1_SD

PHY 1 fiber mode Signal Detect

Same P0_SD description

P1_ACT\

P1_FIBER

B5/4m

PHY 1 Link/Activity LED

This pin is input direction during chip reset stage used to bootstrap the mode

setting to decide the PHY 1 media mode, please refer to Section 3.1

RSET_BG

PHY off-chip Bias Resistor

Connects an external resistor of 12 KΩ ± 1% to the PCB analog ground.

Table 1-2: Ethernet PHY Pin Description

Pin Name

Type

Pin No

Pin Description

VCC3IO

10, 45,

65, 77

Digital Power for I/O pins, 3.3V

Please add a 0.1uF bypass capacitor between each VCC3IO and GND.

VCCK

5, 16, 29,

46, 55, 72

Digital Power for core, 1.2V

Please add a 0.1uF bypass capacitor between each VCCK and GND.

VCC33A

22, 28,

32, 39

Analog Power for Ethernet PHY, 3.3V

Please add a 0.1uF bypass capacitor between VCC33A and GND.

VCC12A_PLL

Analog Power for PLL, 1.2V.

Please add a 0.1uF bypass capacitor between VCC12A_PLL and GND.

GND

EPAD

Ground for all Analog and Digital Power.

Table 1-3: Power/Ground Pin Description

AX58100LT Datasheet(PDF) 11 Page - ASIX Electronics Corporation

AX58100LT Datasheet(HTML) 11 Page - ASIX Electronics Corporation

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