AX58100LT datasheet(16/71 Pages) ASIX

16 / 71 page

AX58100

EtherCAT Slave Controller

I/O Watchdog

The I/O Watchdog is for AX58100 safety engine and used to monitor I/O signals toggle status, and an emergency

stop input (EMn) pin.When I/O signals don't match a pattern or keeping over excepted time, the watchdog will be

triggered, or EMn input pin asserted, force I/O pads enter default level. The default level is configurable, could be

driven low, high or Tristate.

PWM Controller

The PWM control module provides Pulse Width Modulation (PWM), and alternatively STEP / DIR to control

motor driving. The PWM mode has eight pins (three pairs control signal, each control signal pair has a high pulse

pin (PWMxH), and low pulse pin (PWMxL) control power drive circuit. Another has two alignment pins, PULZ

and PULC point cycle start and central time, three programmable trigger pins, PULA PULB and PULAB. The step

pulse mode has 2 pins, step (STEP) and direction (DIR) connect to step motor controller, share PWM1H/L pins.

The PWM supports up to 12.5MHz output frequency, and programmable polarity, timing adjustment.

Incremental and Hall Encoder Interface

TheAX58100 provides an interface with a linear or rotary incremental encoder to get position information, support

four input modes. The Sin/Cos mode (A / B / Z pins), Clock-Wise mode (CW / CCW / Z pins), Direction-Clock

mode (DIR / CLK / Z pins), and the Hall mode (A / B / C pins). It can accumulate positions in three modes,

Sin/Cos, Clock-Wise and Direction-Clock modes, and calculates the GAP time in Hall mode.

The Sin/Cos mode supports input frequency up to 8.33MHz, CW/CCW, and DIR/CLK up to 16.66MHz, and the

Hall mode up to 2.77MHz respectively.

SPI Master Controller

The Serial Peripheral Interface (SPI) master controller provides a full-duplex, synchronous serial communication

interface (4 wires) to flexibly work with numerous SPI peripheral devices or microcontroller with the SPI slave.

The SPI master controller supports 4 types of interface timing modes, namely, mode 0, 1, 2, and 3 to allow working

with most SPI devices available. It supports MSB/LSB first data transfer.

Supports 8 channels could sequential access per device, variable transfer length up to 8 bytes each channel.

Support multi-channel access to the same device, the data length could be up to 64bytes. For high performance

applications, the SPI master controller supports continues transfer data between the SPI device and data registers.

Provide 4 chip select, support one-cold encode output (up to 4 devices), or use binary encode output (use an

external binary decoder) up to 8 devices.

Support standard SPI device access without glue logic circuit. Support “trigger data ready input” for ADC

application, support “data loaded indication out” and “data path daisy chain” for DAC application.

The MSCLK SPI clock is programmable by software and can run up to 50MHz.

AX58100LT Datasheet(PDF) 16 Page - ASIX Electronics Corporation