AX58100LT datasheet(7/71 Pages) ASIX

7 / 71 page

AX58100

EtherCAT Slave Controller

List of Tables

TABLE 1-1: COMMON PIN DESCRIPTION............................................................................................................................10

TABLE 1-2: ETHERNET PHY PIN DESCRIPTION .................................................................................................................11

TABLE 1-3: POWER/GROUND PIN DESCRIPTION ................................................................................................................11

TABLE 1-4: PDI DIGITAL I/O, GPIO PIN DESCRIPTION .....................................................................................................12

TABLE 1-5: PDI SPI SLAVE INTERFACE PIN DESCRIPTION................................................................................................12

TABLE 1-6: PDI LOCAL BUS INTERFACE PIN DESCRIPTION ..............................................................................................13

TABLE 1-7: PWM MOTOR CONTROLLER PIN DESCRIPTION ..............................................................................................13

TABLE 1-8: INCREMENTAL/HALL ENCODER INTERFACE PIN DESCRIPTION.......................................................................13

TABLE 1-9: SPI MASTER PIN DESCRIPTION.......................................................................................................................14

TABLE 1-10: PORT 2 MII PIN DESCRIPTION ......................................................................................................................14

TABLE 3-1: BOOTSTRAP PINS CONFIGURATION ................................................................................................................17

TABLE 3-2: ESC MEMORY MAP........................................................................................................................................31

TABLE 3-3: FUNCTION REGISTER MAP..............................................................................................................................33

TABLE 3-4: ESC MEMORY AND FUNCTION REGITERS MIRROR MAPPING TABLE .............................................................35

TABLE 4-1: POWER CONSUMPTION ...................................................................................................................................38

TABLE 4-2: THERMAL CHARACTERISTICS .........................................................................................................................38

TABLE 4-3: POWER ON RESET (POR) TIMING TABLE .......................................................................................................39

TABLE 4-4: POWER-UP SEQUENCE TIMING TABLE ............................................................................................................40

TABLE 4-5: I2C EEPROM TIMING TABLE.........................................................................................................................42

TABLE 4-6: PORT 2 MII TX TIMING TABLE ......................................................................................................................43

TABLE 4-7: PORT 2 MII RX TIMING TABLE ......................................................................................................................44

TABLE 4-8: MDC/MDIO TIMING TABLE ..........................................................................................................................45

TABLE 4-9: DC SYNC/LATCH TIMING CHARACTERISTICS..............................................................................................46

TABLE 4-10: DIGITAL I/O TIMING TABLE..........................................................................................................................48

TABLE 4-11 PDI SPI SLAVE TIMING TABLE......................................................................................................................49

TABLE 4-12: FUNCTION SPI WITH SHARE PIN TIMING TABLE............................................................................................54

TABLE 4-13: FUNCTION SPI WITH INDIVIDUAL PIN TIMING TABLE ...................................................................................54

TABLE 4-14: PDI LOCAL BUS TIMING TABLE ...................................................................................................................58

TABLE 4-15: FUNCTION LOCAL BUS ACCESS TIMING .......................................................................................................60

TABLE 4-16: PWMX TIMING TABLE .................................................................................................................................61

TABLE 4-17: PWMX SHIFT TIMIN TABLE .........................................................................................................................62

TABLE 4-18: PWMX BBM TIMING TABLE .......................................................................................................................63

TABLE 4-19: STEP FUNCTION TIMING TABLE .....................................................................................................................63

TABLE 4-20: INCREMENTAL AND HALL ENCODER TIMING TABLE ....................................................................................65

TABLE 4-21: SPI MASTER TIMING TABLE.........................................................................................................................68

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