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RT3052F Datasheet(PDF) 96 Page - List of Unclassifed Manufacturers |
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RT3052F Datasheet(HTML) 96 Page - List of Unclassifed Manufacturers |
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96 / 235 page  RT3050/52 Datasheet Preliminary Revision August 14, 2008 DSR3050/52_V.2.0_081408 -96- Form No.：QS-073-F02 Rev.：1 Kept by： DCC Ret. T ime： 5 Years FE_RST_GLO: Frame Engine Global Reset (offset: 0x0C) Bits Type Name Description Initial value 31:16 RC FC_DROP_CNT Flow control drop packet count. 16’b0 15:1 - - Reserved 15’b0 0 WO PSE_RESET PSE reset Write 1 to reset PSE Write 0 to disable reset PSE 1’b0 FE_INT_STATUS: Frame Engine Interrupt Status (offset: 0x10) Bits Type Name Description Initial value 31 R/W CNT_PPE_AF PPE Counter Table Almost Full Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 30 - - Reserved 1’b0 29 R/W CNT_GDM_AF GDMA 1 &2 Counter Table Almost Full Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 28:25 - - Reserved 4’b0 26 R/W PSE_P2_FC PSE port2 (GDMA 2) flow control asserted. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 25 R/W GDM_CRC_DROP GDMA 1 & 2 discard a packet due to CRC error Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 24 R/W PSE_BUF_DROP PSE discards a packet due to buffer sharing limitation (flow control) Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 23 R/W GDM_OTHER_DR OP GDMA 1 & 2 discard a packet due to other reason (e.g. too short, too long, FIFO overflow, checksum error,.., etc.) Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 22 R/W PSE_P1_FC PSE port1 (GDMA 1) flow control asserted. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 21 R/W PSE_P0_FC PSE port0 (CDMA) flow control asserted. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 20 R/W PSE_FQ_EMPTY PSE free Q empty threshold reached & forced drop condition occurred. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 17 R/W TX_COHERENT TX_DMA finds data coherent event when checking ddone bit. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 16 R/W RX_COHERENT RX_DMA finds data coherent event when checking ddone bit. Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 15:12 - - Reserved 4’b0 11 R/W TX_DO NE_INT3 Tx queue#3 packet transmit interrupt Write 1 to clear the interrupt. Read to get the raw interrupt status 1’b0 10 R/W TX_DO NE_INT2 Tx queue#2 packet transmit interrupt Write 1 to clear the interrupt. 1’b0 |
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