RT3052F datasheet(46/235 Pages) ETC1

46 / 235 page

RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-46-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

3.7 UART

3.7.1

Features



16550-compatible register set, except for Divisor Latch register



5-8 data bits



1-2 stop bits (1 or 2 stop bits are supported with 5 data bits)



Even, odd, stick or no parity



All standard baud rates from 40 b/s to 2.5 Mb/s



16-byte receive buffer



16-byte transmit buffer



Receive buffer threshold interrupt



Transmit buffer threshold interrupt



False start bit detection in asynchronous mode



Internal diagnostic capabilities



Break simulation

3.7.2

Loop-back control for communications link fault isolation

Block Diagram

Fig. 3-7-1 UART Block Diagram

3.7.3

RBR: Receive Buffer Register (offs et: 0x00)

Bits

Type

Name

Description

Initial value

31:8

Reserved

24’b0

RXD[7:0]

Receive Buffer Data

Receive data. Data is transferred to this register from the rec eive

shift register after a full character is received. The O E bit in the

LSR register is set, indication a receive buffer overrun, if the

contents of this register has not been read before another

character is received.

1’b0

TBR: Transmit Buffer Register (offset: 0x04)

Bits

Type

Name

Description

Initial value

31:8

Reserved

24’b0

TXD[7:0]

Transmit Buffer Data

Transmit data. When a character is written to this register, it is

stored in the transmitter holding register; if the transmitter

1’b0

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