RT3052F datasheet(21/235 Pages) ETC1

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RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-21-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

1.4 Boot strapping Signal description

Pin Name

Boot Strapping Signal

Name

Description

MA7..MA0

TEST_CODE[7:0]

A vec tor to set CHIP operation/testing modes.

In normal operation, please use the default value :

8’b00000000

{MA9, MA8}

BOOT_FRO M

2’b00 : boot from external 16-bit flash (default)

2’b01 : boot from external 8-bit flash

2’b10 : boot from external NAND flash

2’b11 : boot from internal ROM

MA10

CPU_CLK_SEL

1’b0 : Low (320Mhz)

1’b1 : High (384Mhz, default)

MA12

BIG_ENDIAN

0 : Little Endian (default)

1 : Big Endian

MA13

BYPASS_PLL

0 : Do Not Bypass PLL (default)

1: Bypass PLL

MA14

BOOT_ADDR

0 : CPU boots at address 0x1FC00000(default)

1 : CPU boots at address 0x1F000000

{MA17,MA16}

GE_MODE

Gigabit Port Mode

2’b00 : RGMII Mode (10/100/1000M bps)

2’b01 : MII Mode (10/100 Mbps)

2’b10 : Reversed MII Mode (10/100 Mbps)

2’b11 : Reserve

MA20

INIC_8MB_SDRAM

0 : INIC SDRAM size is 2MB (default)

1 : INIC SDRAM size is 8MB

MA21

INIC_EE_SDRAM

0 : Take INIC SDRAM size from INIC_8MB setting (default)

1 : Take INIC SDRAM size from EEPROM

RT3052F Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers

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